1. Field of the Invention
This invention relates to a shift system, and more particularly to a shift system in which input data is shifted by a multiple of 2.sup.A and then by 0 to 2.sup.A -1.
2. Description of the Prior Art
In general, a data processor comprises a main memory 1, a memory control unit 2, an instruction control unit 3, an execution processing unit 4, a channel unit 5 and a console 6, as shown in FIG. 1. For one of the internal functions of the execution processing unit 4, a shift circuit is provided.
The shift circuit shifts input data, by a certain amount, to the right or left for output. For example, as shown in FIG. 2(a), data A to R applied to an input part 7 are shifted by three bits to the right for transfer to an output part 8, from which the shifted data are removed. At this time, three bits of the output data on the left hand side thereof are 0.
With this method, however, when the number of data bits is large, it is difficult to get the shift circuit on one chip and it is necessary to use a plurality of chips, for example, I and II as shown in FIG. 2(b). Consequently, an interface is required between the chips I and II, and an increase in the amount of data to be shifted causes a corresponding increase in the amount of data to be interfaced. In the case of FIG. 2(b), three interface lines F--F, G--G and H--H from an input part 7-1 to an output part 8-2 will be necessary. For example, when the data is shifted to right by eight bits an 8 bit interface is required between the chips for each to shift from the input part 7-1 to the output part 8-2; further, if taking into account the need for a left shift, too, 8 bit interface is needed between the chips for each in the left direction to shift from an input part 7-2 to an output part 8-1. In this way, depending on the amount of data shifted and the direction of shift, the number of data interface lines becomes very large and a large number of pins are required to be connected between the chips.
When the signals transmited to the output parts 8-1 and 8-2 are outputted as they are, a time lag, caused by the interface does not matter substantially. But when the data A to R are arranged in a 4-bit shift configuration and the data is shifted in a plurality of 4 bit stages, for example, when the data is shifted to the output parts 8-1 and 8-2 by steps of four bits first and then by one bit, the time lag caused by the interface based on a chip-to-chip interface cross in each stage causes a serious degradation of the processing speed.
In order to prevent the lowering of the processing speed resulting from the time lag, it is necessary to provide on the chip II another input part for receiving the data from F to R in the case of FIG. 2(b). Therefore, in this case, when taking into consideration the leftward shift and the contruction of the chips I and II the, inputting of all input data A to R to both of the chips I and II involves redundant gates and a lot of input-output pins on the chips.